Multiple asynchronous first-in-first-out (FIFO) buffers are sometimes used in applications where it is desired to use data from domains that operate on two clocks that have the same frequency but, have an unknown phase relationship. For each buffer, one of the clocks, called the write clock, is used to write into the FIFO buffer element, and the other clock, called the read clock, is used to read the data from the buffer element. In such an arrangement, write and read operations are necessarily separated in time in order to accommodate the potential phase differences of the two clocks. In systems using multiple FIFO buffer elements, the write clocks and the data to be written may be aligned, but the read clocks may be of arbitrary phase. Accordingly, when more than one buffer element is used in a system, delay due to the potential time differential, also called skew, can result. Data skew is defined herein for the purposes of illustrating the invention as the maximum possible time difference between the time data is read out of the first FIFO element and the time data is read out of the second FIFO element. Skew causes a system to perform more slowly, resulting in decreased throughput and ultimately in higher costs.
Due to these and other problems, improved systems and methods for reading and writing data with reduced skew in systems using multiple FIFO buffer elements would be useful and desirable in the arts.